A processor (MPU: Micro Processing Unit) including a plurality of CPU (Central Processing Unit) cores for embedding usage that is composed of a multicore has been developed. These processors are formed in one chip including peripheral devices. A technique of operating several different OSs (Operating System) on a multicore CPU is known. Further, a means to notify a single interrupt request (IRQ: Interrupt ReQuest) to a plurality of CPU cores is known as a function of an MPU. Furthermore, the MPU can be configured to assign which interrupt request to which CPU core according to register setting.
Additionally, for example, as shown in FIG. 8, a technique of transferring audio data via an I2S (Inter-IC Sound) bus from a CPU inside a MPU 50 to an ADAC (Audio DAC) 51 is known. The audio data is PCM (Pulse Code Modulation) audio, for example. Note that I2S is a serial communication format manufactured by PHILIPS (registered trademark) which forms an interface device of the audio data. In the I2S standard, PCM audio and compressed audio (such as μ-law and ADPCM) can be output to the ADAC 51 via the I2S bus. Moreover, in FIG. 8, the I2C (Inter-Integrated Circuit) bus is a serial bus for device control developed by PHILIPS (registered trademark). The ADAC 51 converts the audio data into stereo audio. A DAC is a D/A Converter. Analog audio (stereo) output from the ADAC 51 is played via a speaker.
In addition, an I2S device including a FIFO (First In First Out) buffer is known. Such an I2C device dequeues audio data stored to the FIFO buffer and outputs it to an ADAC via an I2S bus. Then, when the size of data, which is dequeued from the FIFO buffer and reduced, reaches boundaries such as 4, 8, 16, and 32 bytes, there is the IS2 device that can generate an interrupt (hereinafter referred to as a “FIFO boundary interrupt”). Generally, this interrupt is used for PIO (Programmed Input/Output) transfer.